Actel offers the Varicore compiler, available both for Windows NT and for UNIX, capable of creating an efficient automatic place and route stage.

The EPGA blocks can then be tested and verified after having been entered into a SoC project. The EPGA blocks have an internal self test function, that permits the control of efficiency and operation, as well as evaluating the positioning of the pins managing up to 1280 I/O ports per nucleus. The VariCore compiler supports projects developed with RTL flow technology, both in VHDL format and in Verilog format.

In terms of synthesis VeriCore is supported by Synopsys’ Design. As far as the testing of the project is concerned, in terms of front-end, Varicore Compiler supports VHDL Verilo and Vital type simulations and is compatible with the tools and the performance, in terms of simulation of Synonpsys’ Prime Time and PrimePower. For that which concerns the physical project (of the layout) are supplied coming from the VariCore Compiler in GDSII format files, compatible with the Cadence Virtuoso software and Avant! Apollo software.