It must be kept in mind that up to now many factories still used manufacturing processes with geometries up to 0.25 micron with 100 millimetres silicon wafers. Going under the limit of 0.1 micron can start off a few problems just as much as the use of large section wafers use activates others.

New geometries
The passage to silicon geometries lower than 0.25 micron introduces the concept of sub wavelength gap. The wavelength size associated to the light used to make the various geometries become comparable, with the size of cells to be made in silicon. This is a problem of considerable entity, since this would make traditional processes to develop solutions of 0.12 micron and over literally unusable.

Phase-shift technology
Numerical Technology, acquired in October 2000 by Cadabra has prepared a technology called phase-shift. The solution enables using 248 nm steppers, instead of having to buy new ones, by factories already capable of producing 0.25 micron integrated circuits, and not having to create a new photolithography process: a saving of about 400 million dollars for a middle-sized system. The project chart is set up by Santa Clara’s company technicians, providers of GDS II format output, the most used market standard.

Setting power through architecture
The development of capacity chips, in terms of equivalent gates, that are always greater is undoubtedly one of the most recurring themes emerged. Work groups didn’t always have enough experience to optimise a low power project, and especially there aren’t many automatic reduction systems during the planning of dissipated power. SoC development within market-acceptable times requires the capacity to determine the power the chip will dissipate when it is still being designed, before it reaches design levels in gate terms. Basically it is necessary to intervene at RTL design level.

According to the figures made available by some of these software producers about 80% of the power the chip will dissipate is caused by the architecture, and therefore to intervene on RTL design to minimise this dissipation represents a valid alternative to the chip’s complete re-design. Owing to this solution it will therefore be possible to optimise (before the physical realisation) the chip’s design, arriving at real cases where an abatement of the dissipated power is obtained of 25-50% (Sequence figures) in large capacity chips in terms of equivalent gates), whereas operators at only synthesis based methods level succeed in obtaining (Sequence figures) values of maximum 5-10%.

October.2001