Lattice has announced the development of second generation high density PLD 3,3V SuperFasttm BFW.

This is the ispLSI 2000VE family, made up of five devices, offering logical densities from 32 macrocells to 192 macrocells and boasts the SuperFast Lattice superfast architecture.

The ispLSI 2032VE device increases PLD speed to 300MHz (Fmax) with pin-to-pin speed (Tpd) of 3ns.

In the progressing need for higher frequencies of the system clock, faster logical times acquire critical importance.

Second generation ispLSI 2000VE also boast faster entry/exit times of any CPLD 3,3V, with set-up input-to-clock times of 2,0 ns (T su) and clock-to-output delays of 2,0 ns (Tco).

These latter performances, owing to the use of advanced silicon sub-micron E2CMOS technology, are in fact a third faster than other 3,3V and they eliminate critical bottlenecks in system performance.

The entire ispLSI 2000VE family offers a complete range of packages that enable space saving on the card, from the traditional Plcc (Plastic leaded chip carrier) and Pqfp/Tqfp (plastic/thin quad flat packs) to Fpbga (fine-pitch ball grid arrays).