Hitachi Semiconductor (America) Inc. announced a new data storage product, the "superAND" flash memory. They are the industry's first devices to combine single-voltage programmable flash cells with built-in memory management function. The chips are designed to lower overall system cost and allow easier integration to small mobile products such as cellular phones, PDAs and digital cameras.The compact, economical 128-Megabit (16-Megabyte) superAND flash memory chips are available in 1.8-Volt and 3.3-Volt versions with x16 organizations, and in a 3.3-Volt version with a x8 organization. To ease system design, the flash devices have the popular NAND-type interface. Customers can gain benefits by applying them in designs that previously used NAND-type flash chips, without the memory management overhead burden that standard NAND flash memory imposes on the CPU. The superAND flash products have pin assignment and command-signal compatibility with NAND flash memory. In addition, the new flash products support a power-on read function that allows a system to boot directly from the superAND memory without the need for an external ROM.
Built-in memory management maximizes reliability, operating life
By carefully designing the memory management logic included in the superAND products, Hitachi engineers implemented various key functions while only increasing chip area by few percent. As a result, the superAND chip has a compact die size, enabling a reasonable price.
The control logic is precisely matched to the characteristics and operation of the two-bit-per-cell flash cells and performs two basic flash functions. First, it locks out defective memory sectors, ensuring error-free performance of the memory area. Should abnormalities occur during operation, the built-in memory management logic detects the malfunctions and automatically replaces defective sectors with reserved sectors to ensure the integrity of the stored data. The superAND flash eliminates the need of external ECC (error correction code) and other memory management algorithms.
Second, it performs on-chip wear leveling. This maximizes the endurance, or life span, of the flash memory. It increases the total number of read/write cycles the device achieves by ensuring that writes are distributed throughout the memory array, not concentrated in any particular section of flash cells.
The superAND devices also provide two other features that can be useful to system designers. They support a power-on read function. When a system is powered on, up to 2 kilobytes (2 KB) of data can be read directly from the superAND flash without inputting any command or address. They also support a deep-standby function for extremely tight power supply control. In deep standby mode, the current of the superAND chip is only 5 microamps, which can extend battery life.
To help customers design systems using the new flash memory, Hitachi will release a VHDL model as the functional description model, an IBIS model as the I/O operation model, and a reference driver model in C language. This suite of support tools will be available in June 2002.
May.2002
Hitachi Europe
