It enables developers to minimize the size of the code and reduce project, testing and realization times of dedicated applications (embedded) based on the PowerPC MPC7450 microprocessor.

Motorola’s new MPC7450 is a high-performance superscalar RISC processor, optimized for use in next-generation network infrastructures. Green Hills’ IDE MULTI 2000 has an advanced optimized C compiler that simplifies design.

The availability of MULTI 2000 for MPC7450 widens the range of Motorola PowerPC devices that are supported by Green Hills; a support that today includes the MPC5xx, MPC6xx, MPC7xx, MPC8xx, MPC74xx and MPC82xx families. As well as the integrated system environment, Green Hills offers operative systems in real time for dedicated applications with limited resources (ThreadX) or with high-reliability requirements (INTEGRITY), and also an optimized RTOS (Integrity-178B) for critical applications in the telecommunications and defense sector, that require an availability of 99,999% or higher.

A complete range of products for Internet connectivity of dedicated applications, and the full support of a wide range of telecom protocols, enables development simplification through an optimized design for the used RTOS and a visual development environment.

Multi 2000 also includes: an operating error detection system; a version extension mechanism; a performance analyzer; an instruction set simulator that enables programmers to develop and test the PowerPC code on a PC or workstation, without having to physically have the hardware available jon which it will be carried out.

The core of the Multi environment is represented by the source debugger with incremental debug , and it is capable of supporting analysis at a process and system level. The fact that the IDE recognizes the used Rtos enables developers to correct and optimize their applications at task level.

The optimized compiler, included in Multi, automatically subdivides the C programs for an optimal execution on the MPC7450. The compiler automatically analyses the data flow and the data dependencies and reorders, still automatically, the instruction sequence so as to exploit the processor’s dual structure and permit work in parallel of the vector elaboration, in floating and whole points.

The compiler further improves vector elaboration capacities, separating the real and imaginary parts of complex numbers, and arranging them in the memory for the connected vectors to be adjacent.